omla

omla/cup

this project is about pwm generator with a feature of variable duty cycle .

omla/cupa_624

hada_2d1_3

omla/cup_gf180mcuD_mirror

RISC-V based sub system

omla/cup_gf180mcuD_mirror_re

Arduino pin compatible Single RISCV 32 Bit core Project

omla/cuP_load_test

This is a design project led by the Mixed-Signal Analog Circuit Sensor Design group MLAB from University of Tennessee Knoxville. We have worked with five undergraduate students from the EECS department designing an Electrochemical Sensor chip to monitor water quality.

omla/cup_private

Physical Design of a 4 bit bidirectional counter

dlindley/DL_specere_DEV_TO

Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs. It is the heart of Google's TPUs and major workhorses of DSP engines. In this project, we manually build a 3x3 matrix multiplier with Multiply-Accumulate Units that support two popular data formats used in modern machine learning or neural networks applications. FP16 and int8 modes are runtime configurable through the Caravel SoC core. The design is focusing on clean coding for ease of understanding and proper modulation for future extension. Huge shoutout and appreciation to Steve @https://aurifexlabs.com/ for his invaluable assistance with Caravel

omla/dl_spectr_dv

Projeto pmos.

omla/kwsiac

This submission is for Ibtida-I which was selected for the First MPW Shuttle. Due to the issues in the clock tree synthesis in the first shuttle

omla/lvs_test

Simple LED output which is based on an internal counter

mattlongprimary/mbl_dec_11_d

asdf

omla/multi_cells_example

Another push test

omla/ogs_sensor

It Encode data Our priority vice

omla/openframe_timer_mirror

CRISPR/Cas9-induced site-specific DNA double-strand breaks (DSBs) can be repaired by homology-directed repair (HDR) or non-homologous end joining (NHEJ) pathways.

omla/rx-receiver

mcm_8outputs

omla/show_prompt

This project focuses on design of a Current Starved VCO using Google Skywater (sky130) Technology node with operating voltage of 1.8V.

omla/show_prompt_re

We are developing an optimized RV32I processor named RVCoreP

omla/show_prompt_re_2

The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.

omla/test_anton_prob

test_anton_prob

omla/test_anton_prob_real

test_anton_prob_real

omla/test_big_commit

VSCPU3x is a programmable system with 3 VSCPU cores and 24 kB SRAM.

omla/test_cup_push

Implementing the matrix operation of 16-point Walsh Transform using 8-bit inputs.

omla/test_david

test project for aialra

temp-grp/testgrpprj

Conventional lifting based 9/7 DWT using direct implementation.

omla/testingset

LOOKING AT EFABLESS

omla/test_repo_shuttle

test efabless project

omla/test_repo_shuttle_wp

QDI Asynchronous Control-Add Logic Demo

omla/timer_lvs

Uranus eFPGA with nonvolatile config in eFuse array. GFMPW1 rerun with fixes.

omla/tinytp05

Based on the GMP-grade quality management system platform

omla/tt_6

ff

omla/tt_8

The 7 segment LED to help understand the process for our next innovative project. - Rowan Wysocki & Leila Suljevic

omla/unic_ic3

sdfsfsfdfdsfd

omla/vector_compressor

This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide. Address bus is 12 bits wide. The instructions are like old 8086 microprocessors. This tape-out has 8KB on-chip RAM. Targeted for calculator

omla/z2a_mt

A bidirectional counter is a sequential up/down That has the ability to count in both directions Either from some preset value as well as zero. In This up/down counter an external input is used for Using either up or down mode. Counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters.

omla/z2a_mt_re

We have implemented mixed signals blocks: A SAR-ADC with 12b and OSR=1...256 (decimation filter included)

Projects