Logs

                                    STDOUT: Loading Job # 78537535-dcd6-4d07-9273-256d6b6e4510 ...
STDOUT: Commercial Shuttle MPW Precheck | Starting Job # 78537535-dcd6-4d07-9273-256d6b6e4510 ...
STDOUT: {{Project Git Info}} Repository: https:/repositories.dev.efabless.com/omla/dl_spectr_dv.git | Branch: main | Commit: e459756b9558af37977d83f97b0e6a638c6b4b69
STDOUT: {{EXTRACTING FILES}} Extracting compressed files in: dl_spectr_dv.git
STDOUT: {{Project Type Info}} analog
STDOUT: {{Project GDS Info}} user_analog_project_wrapper: 70e01da1628d90589fe653138b508020460112a4
STDOUT: {{Tools Info}} KLayout: v0.29.2 | Magic: v8.3.471
STDOUT: {{PDKs Info}} SKY130A: None | Open PDKs: 6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
STDOUT: {{START}} Precheck Started, the full log 'precheck.log' will be located in '/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs'
STDOUT: {{PRECHECK SEQUENCE}} Precheck will run the following checks: [Makefile, Top Cell Check, Consistency, GPIO-Defines, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea, Spike Check, Illegal Cellname Check, OEB]
STDOUT: {{STEP UPDATE}} Executing Check 1 of 15: Makefile
STDOUT: {{MAKEFILE CHECK PASSED}} Makefile valid.
STDOUT: {{STEP UPDATE}} Executing Check 2 of 15: Top Cell Check
STDOUT: Success: Single top cell 'user_analog_project_wrapper' found in the GDS layout.
STDOUT: {{Top Cell Check CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has exactly 1 topcell.
STDOUT: {{STEP UPDATE}} Executing Check 3 of 15: Consistency
STDOUT: PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
STDOUT: COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (16 instances).
STDOUT: MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
STDOUT: LAYOUT CHECK FAILED: The GDS layout for user_analog_project_wrapper doesn't match the provided structural netlist. Mismatching modules are: ['GSense_Contacts_nFET_3V_1nf$#']
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} user_analog_project_wrapper netlist failed 1 consistency check(s): ['LAYOUT'].
STDOUT: {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
STDOUT: {{STEP UPDATE}} Executing Check 4 of 15: GPIO-Defines
STDOUT: GPIO-DEFINES: Checking verilog/rtl/user_defines.v, parsing files: ['/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_base.v', 'dl_spectr_dv.git/verilog/rtl/user_defines.v', '/opt/checks/gpio_defines_check/verilog_assets/gpio_modes_observe.v']
STDERR: Generating LALR tables
STDERR: WARNING: 183 shift/reduce conflicts
STDOUT: GPIO-DEFINES report path: /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/gpio_defines.report
STDOUT: {{GPIO-DEFINES CHECK PASSED}} The user verilog/rtl/user_defines.v is valid.
STDOUT: {{STEP UPDATE}} Executing Check 5 of 15: XOR
STDOUT: {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/user_analog_project_wrapper.xor.gds
STDOUT: {{XOR CHECK PASSED}} The GDS file has no XOR violations.
STDOUT: {{STEP UPDATE}} Executing Check 6 of 15: Magic DRC
STDOUT: Found 0 violations
STDOUT: 0 DRC violations
STDOUT: {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 7 of 15: Klayout FEOL
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_feol_check.xml -rd thr=8 -rd feol=true >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_feol_check.log
STDOUT: No DRC Violations found
STDOUT: {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 8 of 15: Klayout BEOL
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_beol_check.xml -rd thr=8 -rd beol=true >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_beol_check.log
STDOUT: Total # of DRC violations is 3 Please check /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_beol_check.xml For more details
STDOUT: {{Klayout BEOL CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 9 of 15: Klayout Offgrid
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/tech-files/sky130A_mr.drc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_offgrid_check.xml -rd thr=8 -rd offgrid=true >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_offgrid_check.log
STDOUT: Total # of DRC violations is 8 Please check /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_offgrid_check.xml For more details
STDOUT: {{Klayout Offgrid CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 10 of 15: Klayout Metal Minimum Clear Area Density
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/drc_checks/klayout/met_min_ca_density.lydrc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_met_min_ca_density_check.xml -rd thr=8 >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_met_min_ca_density_check.log
STDOUT: No DRC Violations found
STDOUT: {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 11 of 15: Klayout Pin Label Purposes Overlapping Drawing
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/drc_checks/klayout/pin_label_purposes_overlapping_drawing.rb.drc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_pin_label_purposes_overlapping_drawing_check.xml -rd thr=8 -rd top_cell_name=user_analog_project_wrapper >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_pin_label_purposes_overlapping_drawing_check.log
STDOUT: No DRC Violations found
STDOUT: {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 12 of 15: Klayout ZeroArea
STDOUT: in CUSTOM klayout_gds_drc_check
STDOUT: run: klayout -b -r /opt/checks/drc_checks/klayout/zeroarea.rb.drc -rd input=dl_spectr_dv.git/gds/user_analog_project_wrapper.gds -rd topcell=user_analog_project_wrapper -rd report=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/klayout_zeroarea_check.xml -rd thr=8 -rd cleaned_output=/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/user_analog_project_wrapper_no_zero_areas.gds >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_zeroarea_check.log
STDOUT: ERROR klayout_zeroarea FAILED, stat=2, see /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/klayout_zeroarea_check.log
STDOUT: {{Klayout ZeroArea CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 13 of 15: Spike Check
STDOUT: run: bash /opt/checks/spike_check/gdsArea0 -V -m /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/outputs/reports/spike_check.xml dl_spectr_dv.git/gds/user_analog_project_wrapper.gds >& /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/spike_check.log
STDOUT: ERROR Spike check FAILED, stat=6, see /mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs/spike_check.log
STDOUT: {{Spike Check CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has spike errors.
STDOUT: {{STEP UPDATE}} Executing Check 14 of 15: Illegal Cellname Check
STDOUT: Found '#' in subcell: GSense_Contacts_nFET_3V_1nf$#
STDOUT: Found '#' in subcell: GSense_Contacts_nFET_3V_1nf$#
STDOUT: Found '#' in subcell: GSense_Contacts_nFET_3V_1nf$#
STDOUT: Found '#' in subcell: GSense_Contacts_nFET_3V_1nf$#
STDOUT: Found '#' in subcell: GSense_Contacts_nFET_3V_1nf$#
STDOUT: {{Illegal Cellname Check CHECK FAILED}} The GDS file, user_analog_project_wrapper.gds, has Illegal Cellnames.
STDOUT: {{STEP UPDATE}} Executing Check 15 of 15: OEB
STDOUT: ERROR OEB FAILED, Could not find LVS configuration file dl_spectr_dv.git/lvs/user_analog_project_wrapper/lvs_config.json
STDOUT: {{OEB CHECK FAILED}} The design, user_analog_project_wrapper, has OEB violations.
STDOUT: {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in '/mnt/users_data/jobs/omla/dl_spectr_dv/78537535-dcd6-4d07-9273-256d6b6e4510/logs'
STDOUT: {{FAILURE}} 7 Check(s) Failed: ['Consistency', 'Klayout BEOL', 'Klayout Offgrid', 'Klayout ZeroArea', 'Spike Check', 'Illegal Cellname Check', 'OEB'] !!!